The present invention relates to semiconductor device fabrication, and more particularly, to a method for fabricating a recess gate in a semiconductor device.
In the fabrication of a semiconductor device, a planar gate forming method is used to form a gate on a planar active region. However, the channel length decreases due to a reduction in the pattern size and the electric field increases due to an increase in the ion implant doping concentration of the substrate, thus causing a junction leakage. This makes it difficult to obtain the refresh characteristics of the device.
In order to solve the above limitation, a three-dimensional recess gate process has been proposed as an alternative gate forming method that forms a gate after etching an active region. The recess gate process makes it possible to increase the channel length and reduce the ion implant doping concentration, thus improving the refresh characteristics of the device.
FIGS. 1A to 1C illustrate a method for fabricating a recess gate in a semiconductor device in accordance with the conventional art. Herein, the right portion of each figure is a cross-sectional view taken along line I-I′.
Referring to FIG. 1A, a device isolation region of a silicon substrate 11 is etched to form a trench 12, and a device isolation layer 13 is formed in the trench 12. This process is called a Silicon Trench Isolation (STI) process.
An amorphous carbon layer 14 is formed on the resulting structure and a mask process for formation of a recess region is performed on the amorphous carbon layer 14, thereby forming a photoresist pattern 15.
The amorphous carbon layer 14 is etched using the photoresist pattern 15 as an etch barrier.
Referring to FIG. 1B, using the amorphous carbon layer 14 as an etch barrier, the silicon substrate 11 is etched to form a recess region 16 that serves as a channel of a transistor. The recess region 16 is also called a recess channel.
Referring to FIG. 1C, a gate insulating layer 17 is formed on the silicon substrate 11 including the recess region 16. A conductive layer is deposited on the gate insulating layer 17 until the recess region 16 is filled, and the deposited conductive layer is etched to form a gate electrode 18.
However, during the ultrafine patternization process of the semiconductor device, a bottom profile of the recess region 16 forms a V-shaped profile in a plasma etching process due to a decrease in the size capable of forming a recess region of a three-dimensional recess gate. This causes a horn effect in which a silicon (Si) residue, referred to as horn H, resides in an upper region adjacent to the device isolation layer 13. The silicon residue is generated by a polymer obtained by redeposition of the carbon of the amorphous carbon layer.
FIG. 2 illustrates a Scanning Electron Microscope (SEM) picture showing horns in accordance with the conventional art. It can be seen from FIG. 2 that the horns reside in an upper region adjacent to a device isolation layer.
The horn H causes degradation of the gate insulating layer 17. The horn H is a stress concentration point and acts as a leakage current source, thereby reducing the device production yield and making it difficult to manufacture DRAMs.
The horn H is caused by the V-shaped profile of the recess region 16 that is formed when the sidewall of the trench 12, which is gap-filled with the device isolation layer 13, is formed at an angle of approximately 90° or less (see FIG. 3).
FIG. 3 illustrates an SEM picture showing a sidewall angle of a trench that is gap-filled with a device isolation layer in accordance with the conventional art. It can be seen from FIG. 3 that the trench is formed at an angle of approximately 90° or less.